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CS5368
114 dB, 192 kHz, 8-Channel A/D Converter
Overall Features
! Advanced Multi-bit Delta-Sigma Architecture ! 24-Bit Conversion ! 114 dB Dynamic Range ! -105 dB THD+N ! Supports Audio Sample Rates up to 216 kHz ! Selectable Audio Interface Formats ! Separate 1.8 V to 5 V Logic Supplie s for
Control and Serial Ports
! High-Pass Filter for DC Offset Calibration ! Overflow Detection ! Pin-Compatible with the 4-Channel CS5364
and 6-Channel CS5366
- -
Left-Justified, IS, TDM 8-channel TDM Interface Formats
Additional Control Port Features
! Supports Standard IC or SPI Control Interface ! Individual Channel HPF Disable ! Overflow Detection for Individual Channels ! Mute Control for Individual Channels ! Independent Power-Down Control per Channel
! Low Latency Digital Filter ! Less than 600 mW Power Consumption ! On-Chip Oscillator Driver ! Operation as System Clock Master or Slave ! Differential Analog Architecture
Pair
VA 5V
VD 3.3 - 5V
VLC 1.8 - 5V
Configuration Registers
Control Interface I2C,SPI or Pins
Level Translator
Internal Oscillator
Device Control
Voltage Reference
8 Differential Analog Inputs
Multi-Bit ADC
Decimation Filter
High Pass Filter
Serial Audio Out PCM or TD M
Level Translator
Digital Audio
VLS 1.8 - 5V
Advanced Product Information
http://www.cirrus.com
This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice.
Copyright (c) Cirrus Logic, Inc. 2005 (All Rights Reserved)
JULY '05 DS624A1
CS5368
Description
The CS5368 is a complete 8-channel analog-to-digital converter for digital audio systems. It performs sampling, analog-to-digital conversion and anti-alias filtering, generating 24-bit values for all 8-channel inputs in serial form at sample rates up to 216 kHz per channel. The CS5368 uses a 5th-order, multi-bit delta sigma modulator followed by low latency digital filtering and decimation, which removes the need for an external anti-aliasing filter. The ADC uses a differential input architecture which provides excellent noise rejection. Dedicated level translators for the Serial Port and Control Port allow seamless interfacing between the CS5368 and other devices operating over a wide range of logic levels. In addition, an on-chip oscillator driver provides clocking flexibility and simplifies design. The CS5368 is the industry's first audio A/D to support a high-speed TDM interface which provides a serial output of 8 channels of audio data with sample rates up to 216 kHz within a single data stream. It further reduces layout complexity and relieves input/output constraints in digital signal processors. The CS5368 is ideal for high-end and pro-audio systems requiring unrivaled sound quality, transparent conversion, wide dynamic range and negligible distortion, such as A/V receivers, digital mixing consoles, multi-channel recorders, outboard converters, digital effect processors, and automotive audio systems. ORDERING INFORMATION Product Description
CS5368 114 dB, 192 kHz, 8-channel A/D Converter
Package Pb-Free
48-pin LQFP YES
Grade
Commercial Automotive
Temp Range Container
-10 to +85C -40 to +85C Tray Tape & Reel Tray Tape & Reel
Order #
CS5368-CQZ CS5368-CQZR CS5368-DQZ CS5368-DQZR
CDB5368
Evaluation Board for CS5368
CDB5368
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CS5368 TABLE OF CONTENTS
1. PIN DESCRIPTION ...................................................................................................... 9 2. CHARACTERISTICS AND SPECIFICATIONS.......................................................... 13
Specified Operating Conditions .............................................................................................. 13 Absolute Ratings .................................................................................................................... 13 System Clocking ..................................................................................................................... 13 Thermal Characteristics.......................................................................................................... 13 DC Power CS5368 ................................................................................................................. 14 Logic Levels ........................................................................................................................... 14 PSRR, Vq and FILT+ Characteristics ..................................................................................... 14 Analog Performance (CS5368-CQZ)...................................................................................... 15 Analog Performance (CS5368-DQZ)...................................................................................... 16 Digital Filter Characteristics ................................................................................................... 17 Serial Audio Interface - IS/LJ Timing ..................................................................................... 18 Serial Audio Interface - TDM Timing....................................................................................... 19 Overflow Timeout ................................................................................................................... 19 Switching Specifications - Control Port - IC Timing ............................................................... 20 Switching Specifications - Control Port - SPI Timing .............................................................. 21
3. TYPICAL CONNECTION DIAGRAM ....................................................................... 23
3.1 Suggested Analog Input Buffer......................................................................................... 24
4. APPLICATIONS ......................................................................................................... 25
4.1 Power ............................................................................................................................... 25 4.2 Clocking ............................................................................................................................ 25 4.3 Stand-Alone Operation ..................................................................................................... 26 4.4 Control-Port Operation ..................................................................................................... 26 4.5 DC Offset Control ............................................................................................................. 26 4.6 Serial Audio Interface (SAI) .............................................................................................. 26 4.6.1 General Description ............................................................................................. 26 4.6.2 Master and Slave Operation ................................................................................ 26 4.6.3 Synchronization of Multiple Devices .................................................................... 27 4.6.4 Sample Rate Ranges........................................................................................... 27 4.6.5 Using M1 and M0 to Set Sampling Parameters................................................... 27 4.6.6 Using DIF1 and DIF0 to Set Serial Audio Interface Format ................................. 28 4.6.7 Master Mode Audio Clocking ............................................................................... 28 4.6.8 Slave Mode Audio Clocking ................................................................................. 28 4.6.9 Master and Slave Clock Frequencies .................................................................. 29 4.7 Serial Audio Formats ........................................................................................................ 30 4.7.1 LJ and IS FORMAT ............................................................................................ 31 4.7.2 TDM Format......................................................................................................... 31 4.8 Overflow Detection ........................................................................................................... 31 4.8.1 Stand-Alone Mode ............................................................................................... 31 4.8.2 Control-Port Mode................................................................................................ 31 4.9 Control Port Operation...................................................................................................... 31 4.9.1 SPI Mode ............................................................................................................. 31 4.9.2 IC Mode .............................................................................................................. 32
5. REGISTER MAP......................................................................................................... 35
5.1 Register Quick Reference ............................................................................................... 35 5.2 00h (REVI) Chip ID Code & Revision Register................................................................. 35 5.3 01h (GCTL) Global Mode Control Register ..................................................................... 35 DS624A1 3
CS5368
5.4 02h (OVFL) Overflow Status Register ............................................................................. 36 5.5 03h (OVFM) Overflow Mask Register .............................................................................. 37 5.6 04h (HPF) High-Pass Filter Register ............................................................................... 37 5.7 05h Reserved .................................................................................................................. 37 5.8 06h (PDN) Power Down Register .................................................................................... 37 5.9 07h Reserved .................................................................................................................. 38 5.10 08h (MUTE) Mute Control Register ................................................................................ 38 5.11 09h Reserved ................................................................................................................ 38 5.12 0Ah (SDEN) SDOUT Enable Control Register .............................................................. 38
Appendix A Digital Filter Plots .................................................................................... 39 Appendix B Parameter Definitions .............................................................................. 43 Appendix C Package Dimensions .............................................................................. 45
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CS5368 LIST OF FIGURES
Figure 1. CS5368 Pinout................................................................................................................. 9 Figure 2. IS/LJ Timing.................................................................................................................. 18 Figure 3. TDM Timing ................................................................................................................... 19 Figure 4. IC Timing ...................................................................................................................... 20 Figure 5. SPI Timing ..................................................................................................................... 21 Figure 6. Typical Connection Diagram.......................................................................................... 23 Figure 7. Recommended Analog Input Buffer............................................................................... 24 Figure 8. Crystal Oscillator Topology ............................................................................................ 25 Figure 9. Master Slave Clock Flow ............................................................................................... 27 Figure 10. Master and Slave Clocking for a 32-Channel Application............................................ 27 Figure 11. Master Mode Clock Dividers ........................................................................................ 28 Figure 12. LJ Format..................................................................................................................... 30 Figure 13. IS Format .................................................................................................................... 30 Figure 14. TDM Format................................................................................................................. 30 Figure 15. SPI Format................................................................................................................... 32 Figure 16. IC Write Format ......................................................................................................... 33 Figure 17. IC Read Format .......................................................................................................... 33 Figure 18. SSM Passband ............................................................................................................ 39 Figure 19. DSM Passband ............................................................................................................ 39 Figure 20. QSM Passband............................................................................................................ 39 Figure 21. SSM Stopband............................................................................................................. 40 Figure 22. DSM Stopband............................................................................................................. 40 Figure 23. QSM Stopband ............................................................................................................ 40 Figure 24. SSM -1 dB Cutoff ......................................................................................................... 41 Figure 25. DSM -1 dB Cutoff......................................................................................................... 41 Figure 26. QSM -1 dB Cutoff......................................................................................................... 41
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CS5368 LIST OF TABLES
Table 1. Overflow Timeout ............................................................................................................ 19 Table 2. M1 and M0 Settings ........................................................................................................ 27 Table 3. DIF1 and DIF0 Pin Settings ............................................................................................ 28 Table 4. Frequencies for 48 kHz Sample Rate using LJ/IS ......................................................... 29 Table 5. Frequencies for 96 kHz Sample Rate using LJ/IS ......................................................... 29 Table 6. Frequencies for 192 kHz Sample Rate using LJ/IS ....................................................... 29 Table 7. Frequencies for 48 kHz Sample Rate using TDM........................................................... 29 Table 8. Frequencies for 96 kHz Sample Rate using TDM........................................................... 30 Table 9. Frequencies for 192 kHz Sample Rate using TDM......................................................... 30 Table 10. Revision History ........................................................................................................... 47
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CS5368 1. PIN DESCRIPTION
M0/SDA/CDOUT M1/SCL/CCLK DIF0/AD0/CS DIF1/AD1/CDIN
AIN1+
AIN5+
AIN6+
AIN1-
AIN5-
AIN6-
MDIV
48 47 46 45 44 43 42 41 40 39 38 37
AIN2+ AIN2GND VA REF_GND FILT+ VQ GND VA GND AIN4+ AIN4-
RST
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
LRCK/FS AIN3+ AIN7+ AIN8+ XTO XTI MCLK AIN3AIN7AIN8GND VX
36 35 34 33
OVFL VLC CLKMODE VD GND SDOUT3/TDM SDOUT1/TDM GND VLS SDOUT2/TDMC SDOUT4/TDMC SCLK
CS5368
32 31 30 29 28 27 26 25
Figure 1. CS5368 Pinout
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CS5368
Pin Name AIN2+AIN2AIN4+AIN4AIN3+AIN3AIN7+AIN7AIN8+AIN8AIN6+AIN6AIN5+AIN5AIN1+AIN1GND VA VQ VX VLS VD VLC REF_GND FILT+ XTIXTO Pin # Pin Description
1,2, 11,12 13,14 15,16 Differential Analog (Inputs) - Audio signals are presented differently to the delta 17,18 sigma modulators via the AIN+/- pins. 43,44 45,46 47,48 3,8 10,19 Ground (Input) Ground reference. Must be connected to analog ground. 29,32 4,9 7 20 28 33 35 5 6 21 22 23 Analog Power (Input) - Positive power supply for the analog section Quiescent Voltage (Output) - Filter connection for the internal quiescent reference voltage. XTAL Power Serial Audio Interface Power - Positive power for the serial audio interface. Digital Power (Input)- Positive power supply for the digital section/ Control Port Interface Power - Positive power for the control port interface. Reference Ground (Input) - For the internal sampling circuits. Positive Voltage Reference (Output) - Reference voltage for internal sampling circuits. Crystal Oscillator Connections (Input/Output) - I/O pins for an external crystal which may be used to generate MCLK. System Master Clock (Input/Output) - When a crystal is used, this pin acts as a buffered MCLK Source (Output). When the oscillator function is not used, this pin acts as an input for the system master clock. In this case, the XTI and XTO pins must be tied low. Serial Audio Channel Clock (Input/Output) In IS mode Serial Audio Channel Select. When high, the odd channels are selected. In LJ mode Serial Audio Channel Select. When low, the odd channels are selected. In TDM Mode a frame sync signal. When high, it marks the beginning of a new frame of serial audio samples. In Slave Mode, this pin acts as an input pin. Main timing clock for the Serial Audio Interface(Input/Output). During Master Mode, this pin acts as an output, and during Slave Mode it acts as an input pin. Serial Audio Data (Output) Channels 7,8. Serial Audio Data (Output) Channels 3,4. Serial Audio Data (Output) Channels 1,2. Serial Audio Data (Output) Channels 5,6. Overflow (Output, open drain) - Detects an overflow condition on both left and right channels. Reset (Input) - The device enters a low power mode when low.
MCLK
LRCK/FS
24
SCLK SDOUT4/TDMC SDOUT2/TDMC SDOUT1/TDM SDOUT3/TDM OVFL RST
25 26 27 30 31 36 41
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CS5368
Stand-Alone Mode CLKMODE DIF1, DIF0 M1, M0 MDIV 34 CLKMODE (Input) Setting this pin HIGH places a divide-by-1.5 circuit in the MCLK path to the core device circuitry.
37, 38 DIF1, DIF0 (Input) - Inputs of the audio interface format. 39,40 Mode Selection (Input) - Determines the operational mode of the device. 42 MCLK Divider (Input) Setting this pin HIGH places a divide-by-2 circuit in the MCLK path to the core device circuitry.
Control Port Mode CLKMODE AD1/CDIN AD0/CS SCL/CCLK SDA/CDOUT MDIV 34 37 38 39 40 42 CLKMODE (Input) This pin is ignored in Control Port Mode and the same functionality is obtained from the corresponding bit in the Global Control Register. Note: Should be connected to GND. IC Format, AD1 (Input) - Forms the device address input AD[1]. SPI Format, CDIN (Input) - Becomes the input data pin. IC Format, ADO (Input) - Forms the device address input AD[0]. SPI Format, CS (Input) - Acts as the active low chip select input. IC Format, SCL (Output) - Acts as the serial clock output from the CS5368. SPI Format, CCLK (Output) - Acts as the serial clock output from the CS5368. IC Format SDA (Input/Output) - Acts as an input/output data pin. SPI Format CDOUT (Output) - Acts as an output only data pin. MCLK Divider (Input) This pin is ignored in Control Port Mode and the same functionality is obtained from the corresponding bit in the Global Control Register. Note: Should be connected to GND.
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CS5368 2. CHARACTERISTICS AND SPECIFICATIONS
All Min/Max characteristics and specifications are guaranteed over the specified operating conditions. Typical performance characteristics and specifications are derived from measurements taken at typical supply voltages and TA = 25C.
SPECIFIED OPERATING CONDITIONS
GND = 0 V, all voltages with respect to 0 V. Parameter DC Power Supplies: Positive Analog Positive Crystal Positive Digital Positive Serial Logic Positive Control Logic (-CQZ) (-DQZ) Symbol VA VX VD VLS VLC TAC TAA Min 4.75 4.75 3.14 1.711 1.71 -10 -40 Typ 5.0 5.0 3.3 3.3 3.3 Max 5.25 5.25 5.25 5.25 5.25 85 85 Unit V V V V V C C
Ambient Operating Temperature
1. TDM Quad-Speed Mode specified to operate correctly at VLS 3.14 V.
ABSOLUTE RATINGS
Operation beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. Transient currents up to 100 mA on the analog input pins will not cause SCR latch-up. Parameter DC Power Supplies: Positive Analog Positive Crystal Positive Digital Positive Serial Logic Positive Control Logic Symbol VA VX VD VLS VLC Iin VIN VIND TA Tstg Min -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -50 -65 Typ Max +6.0 +6.0 +6.0 +6.0 +6.0 10 VA+0.3 VL+0.3 +95 +150 Units V V V V V mA V V C C
Input Current Analog Input Voltage Digital Input Voltage Ambient Operating Temperature (Power Applied) Storage Temperature
SYSTEM CLOCKING
Parameter Input Master Clock Frequency Input Master Clock Duty Cycle Symbol MCLK tclkhl Min 0.512 40 Typ Max 55.05 60 Unit MHz %
THERMAL CHARACTERISTICS
Parameter Allowable Junction Temperature Package Thermal Resistance Symbol Min Typ 48 15 Max 135 Unit C C/W C/W
JA JC
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CS5368 DC POWER CS5368
MCLK = 12.288 MHz; Master Mode. Power Down is defined as RST = LOW with all clocks and data lines held static. GND = 0 V. Parameter Power Supply Current (Normal Operation) VA = 5 V VX = 5 V VD = 5 V VD = 3.3 V VLS, VLC = 5 V VLS, VLC = 3.3 V VA = 5 V VLS, VLC,VD = 5 V Symbol IA IX ID ID IL IL IA ID Min Typ 70 4 88 58 8 5 2 2 830 558 35 Max 77 8 97 64 9 6 915 616 Unit mA mA mA mA mA mA mA mA mW mW mW mW
Power Supply Current (Power-Down)
Power Consumption (Normal Operation) All Supplies = 5 V VA = 5 V, VD = VLS = VLC = 3.3 V (Power-Down)
LOGIC LEVELS
Parameter High-Level Input Voltage Low-Level Input Voltage %VLS/VLC %VLS/VLC Symbol VIH VIL VOH VOL Iin 85 Min 70 Typ -4 logic pins only 10 Max 30 15 Units % % % % mA A
High-Level Output Voltage at 100 A load %VLS/VLC Low-Level Output Voltage at -100 A load %VLS/VLC
OVFL
Current Sink
Input Leakage Current
PSRR, VQ AND FILT+ CHARACTERISTICS
MCLK = 12.288 MHz; Master Mode. Valid with the recommended capacitor values on FILT+ and VQ as shown in the "Typical Connection Diagram". Parameter Power Supply Rejection Ratio at 1 kHz) VQ Nominal Voltage Output Impedance Maximum allowable DC current source/sink Filt+ Nominal Voltage Output Impedance Maximum allowable DC current source/sink Symbol PSRR Min Typ 65 VA/2 25 10 VA 4.4 10 Max Unit dB V k A V k A
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CS5368 ANALOG PERFORMANCE (CS5368-CQZ)
Unless otherwise specified, input test signal is a 1 kHz sine wave. Measurement bandwidth is 10 Hz to 20 kHz. Parameter Single-Speed Mode (Fs = 48 kHz) Dynamic Range Total Harmonic Distortion + Noise referred to typical full scale Double-Speed Mode (Fs = 96 kHz) Dynamic Range A-weighted unweighted 40 kHz bandwidth unweighted -1 dB -20 dB -60 dB -1dB THD+N 108 105 108 105 THD+N HPF enabled HPF disabled (at VA = 5V) CMRR 0 1.07*VA 114 111 108 -105 -91 -51 -102 114 111 108 -105 -91 -51 -102 110 0.1 -99 -99 dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB % ppm/C LSB LSB Vpp k dB A-weighted unweighted -1 dB -20 dB -60 dB THD+N 108 105 114 111 -105 -91 -51 -99 dB dB dB dB dB Symbol Min Typ Max Unit
Total Harmonic Distortion + Noise referred to typical full scale 40 kHz bandwidth Quad-Speed Mode (Fs = 192 kHz) Dynamic Range
A-weighted unweighted 40 kHz bandwidth unweighted -1 dB -20 dB -60 dB -1dB
Total Harmonic Distortion + Noise referred to typical full scale 40 kHz bandwidth Dynamic Performance for All Modes Interchannel Isolation DC Accuracy Interchannel Gain Mismatch Gain Error Gain Drift Offset Error Analog Input Characteristics Full-scale Differential Input Voltage Input Impedance (Differential) Common Mode Rejection Ratio
100
1.13*VA 7.5 82
5
100 1.19*VA -
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CS5368 ANALOG PERFORMANCE (CS5368-DQZ)
Unless otherwise specified, input test signal is a 1 kHz sine wave. Measurement bandwidth is 10 Hz to 20 kHz. Parameter Single-Speed Mode Dynamic Range Total Harmonic Distortion + Noise referred to typical full scale Double-Speed Mode Dynamic Range Fs = 96 kHz A-weighted unweighted 40 kHz bandwidth unweighted -1 dB -20 dB -60 dB -1 dB THD+N 106 103 106 103 THD+N HPF enabled HPF disabled (at VA = 5.0 V) CMRR 0 1.02*VA 114 111 108 -105 -91 -51 -102 114 111 108 -105 -91 -51 -102 110 0.1 -97 -97 dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB % ppm/C LSB LSB Vpp k dB Fs = 48 kHz A-weighted unweighted -1 dB -20 dB -60 dB THD+N 106 103 114 111 -105 -91 -51 -97 dB dB dB dB dB Symbol Min Typ Max Unit
Total Harmonic Distortion + Noise referred to typical full scale 40 kHz bandwidth Quad-Speed Mode Dynamic Range Fs = 192 kHz
A-weighted unweighted 40 kHz bandwidth unweighted -1 dB -20 dB -60 dB -1 dB
Total Harmonic Distortion + Noise referred to typical full scale 40 kHz bandwidth Dynamic Performance for All Modes Interchannel Isolation DC Accuracy Interchannel Gain Mismatch Gain Error Gain Drift Offset Error Analog Input Characteristics Full-scale Input Voltage Input Impedance (Differential) Common Mode Rejection Ratio
100
1.13*VA 7.5 82
7
100 1.24*VA -
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CS5368 DIGITAL FILTER CHARACTERISTICS
Parameter Single-Speed Mode (2 kHz to 54 kHz sample rates) Passband Passband Ripple Stopband Stopband Attenuation Total Group Delay (Fs = Output Sample Rate) Double-Speed Mode (54 kHz to 108 kHz sample rates) Passband Passband Ripple Stopband Stopband Attenuation Total Group Delay (Fs = Output Sample Rate) Quad-Speed Mode (108 kHz to 216 kHz sample rates) Passband Passband Ripple Stopband Stopband Attenuation Total Group Delay (Fs = Output Sample Rate) High-Pass Filter Characteristics Frequency Response Phase Deviation Passband Ripple Filter Settling Time -3.0 dB -0.13 dB @ 20 Hz 1 20 10 10 /Fs
5
Symbol (-0.1 dB)
Min 0 0.58 -95
Typ 12/Fs 9/Fs 5/Fs
Max 0.47 0.035 0.45 0.035 0.24 0.035 0 -
Unit Fs dB Fs dB s Fs dB Fs dB s Fs dB Fs dB s Hz Hz Deg dB s
tgd
0 0.68 -92
(-0.1 dB)
tgd
0 0.78 -92
(-0.1 dB)
tgd
-
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CS5368 SERIAL AUDIO INTERFACE - IS/LJ TIMING
The serial audio port is a three-pin interface consisting of SCLK, LRCK and SDOUT. Logic "0" = GND = 0 V; Logic "1" = VLS; CL = 30 pF, timing threshold is 50% of VLS. Parameter Sample Rates Single-Speed Mode Double-Speed Mode Quad-Speed Mode 1/(64*216 kHz) before SCLK rising after SCLK rising before SCLK rising after SCLK rising Symbol tPERIOD tHIGH tSETUP1 tHOLD1 tSETUP2 tHOLD2 Min 2 54 108 72.3 30 20 20 10 10 Typ 64*Fs Max 54 108 216 70 Unit kHz kHz kHz Hz ns % ns ns ns ns
SCLK Frequency1 SCLK Period SCLK Duty Cycle LRCK setup LRCK hold SDOUT setup SDOUT hold Notes:
1. In Master mode, the SCLK/LRCK ratio is fixed at 64. In Slave Mode, the SCLK/RCLK ratio can be set according to preference. However, chip performance is guaranteed only when using the ratios in Section 4.6.9 Master and Slave Clock Frequencies on page 29.
tPERIOD SCLK tHOLD1 LRCK channel tSET UP1 channel tSETUP2 SDOUT data
Figure 2. IS/LJ Timing
tHIGH
tHOLD2 data
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CS5368 SERIAL AUDIO INTERFACE - TDM TIMING
The serial audio port is a 3 pin interface consisting of SCLK, LRCK and SDOUT. Logic "0" = GND = 0 V; Logic "1" = VLS; CL = 20 pF, timing threshold is 50% of VLS.
Parameter Symbol Min Typ Max Unit
Sample Rates
Single-Speed Mode Double-Speed Mode Quad-Speed Mode1 1/(256*54 kHz) before SCLK rising after SCLK rising in SCLK cycles before SCLK rising after SCLK rising
tPERIOD tHIGH1 tSETUP1 tHOLD1 tHIGH2 tSETUP2 tHOLD2
SCLK Frequency2 SCLK Period SCLK Duty Cycle FS setup FS hold FS width SDOUT setup SDOUT hold
Notes:
2 54 108 72.3 30 20 20 3 10 10
256*Fs -
54 108 216 70 250 -
kHz kHz kHz Hz ns % ns ns ns ns
1. TDM Quad-Speed Mode only specified to operate correctly at VLS 3.14 V. 2. In Master mode, the SCLK/LRCK ratio is fixed at 256. In Slave Mode, the SCLK/RCLK ratio can be set according to preference. However, chip performance is guaranteed only when using the ratios in Section 4.6.9 Master and Slave Clock Frequencies on page 29.
tPERIOD tHIGH1
SCLK tSET UP1 FS tSET UP2 SDOUT data data newframe tHOLD2
tHIGH2 tHOLD1
data
Figure 3. TDM Timing
OVERFLOW TIMEOUT
Logic "0" = GND = 0 V; Logic "1" = VLS; CL = 15 pF, timing threshold is 50% of VLS.
Parameter OVFL time-out on overrange condition Fs = 44.1 kHz Fs = 192 kHz
Table 1. Overflow Timeout
Symbol
Min
Typ
Max
Unit
-
(217-1)/Fs 2972 683
-
ms ms ms
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CS5368 SWITCHING SPECIFICATIONS - CONTROL PORT - IC TIMING
(VLC = 1.8 V - 5.0 V, VLS = VD = 3.3 V, VA = 5.0 V; Inputs: Logic 0 = DGND, Logic 1 = VLC, SDA CL = 30 pF)
Parameter Symbol Min Max Unit
SCL Clock Frequency RST Rising Edge to Start Bus Free Time Between Transmissions Start Condition Hold Time (prior to first clock pulse) Clock Low time Clock High Time Setup Time for Repeated Start Condition SDA Hold Time from SCL Falling SDA Setup time to SCL Rising Rise Time of SCL and SDA Fall Time SCL and SDA Setup Time for Stop Condition Acknowledge Delay from SCL Falling
Notes:
1
fscl tirs tbuf thdst tlow thigh tsust thdd tsud trc tfc tsusp tack
500 4.7 4.0 4.7 4.0 4.7 0 250 4.7 300
100 1 300 1000
kHz ns s s s s s s ns s ns s ns
1. Data must be held for sufficient time to bridge the transition time, tfc, of SCL
RST t Stop irs Re p e at e d Sta rt Sta rt t rd t fd Stop
SDA t buf t hdst t high t hdst t fc t susp
S CL t t t sud t ack t sust t rc
lo w
hdd
Figure 4. IC Timing
20
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CS5368 SWITCHING SPECIFICATIONS - CONTROL PORT - SPI TIMING
(VLC = 1.8 V - 5.0 V, VLS = VD = 3.3 V, VA = 5.0 V; Inputs: Logic 0 = DGND, Logic 1 = VLC, CDOUT CL = 30 pF)
Parameter Symbol Min Max Units
CCLK Clock Frequency RST Rising Edge to CS Falling CS Falling to CCLK Edge CS High Time Between Transmissions CCLK Low Time CCLK High Time CDIN to CCLK Rising Setup Time CCLK Rising to DATA Hold Time1 CCLK Falling to CDOUT Stable Rise Time of CDOUT Fall Time of CDOUT Rise Time of CCLK and CDIN2 Fall Time of CCLK and CDIN3
Notes:
fsck tsrs tcss tcsh tscl tsch tdsu tdh tpd tr1 tf1 tr2 tf2
0 20 20 1.0 66 66 40 15 -
6.0 50 25 25 100 100
MHz ns ns
s
ns ns ns ns ns ns ns ns ns
1. Data must be held for sufficient time to bridge the transition time of CCLK.
2. 3. For fsck <1 MHz For fsck <1 MHz.
RST
tsrs
CS
tcsh tcss tsch tscl tr2
CCLK
tf2 tdsu tdh
CDIN
tpd
CDOUT
Figure 5. SPI Timing
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CS5368 3. TYPICAL CONNECTION DIAGRAM
+
*
1 F 0.01 F
+5V to 3.3V
+5V
+
1 F
0.01 F
5.1
4, 9, 20 33
0.01 F VD
VA
6
220 F 1 F
+
0.1 F 0.1 F
FILT+ VLC REF_GND VQ GND MODE1/SCL/CCLK MODE0/SDA/CDOUT OVFL DIF1/AD1/CDIN DIF0/AD0/CS RST MDIV CLKMODE
35
5 7
0.01 F
39 40 36 37 38 41 42 34
+5V to 1.8V
+
8
Channel 1 Analog Input Buffer
47 48
AIN 1+ AIN 1AIN 2+ AIN 2AIN 3+ AIN 3AIN 4+ AIN 4AIN 5+ AIN 5AIN 6+ AIN 6CS5368
Power Down and Mode Settings
Channel 2 Analog Input Buffer
1 2
Channel 3 Analog Input Buffer
13 14 11
VLS A/D CONVERTER SDOUT3/ TDM SDOUT1/ TDM SDOUT2/ TDMC SDOUT4/ TDMC LRCK/FS SCLK MCLK
28
0.01 F
31 30 27 26 24 25 23
+5V to 1.8V
Channel 4 Analog Input Buffer
12 45 46
Audio Data Processor
Channel 5 Analog Input Buffer
Channel 6 Analog Input Buffer
43
Timing Logic and Clock
44
Channel 7 Analog Input Buffer
15 16 17 18
VX AIN 7+ AIN 7AIN 8+ AIN 8GND
3, 8, 10, 19, 29, 32
20
+5V
* Resistor may only be used if VD is derived from VA. If used, do not drive any other logic from VD.
XTI XTO
21 22
Channel 8 Analog Input Buffer
Figure 6. Typical Connection Diagram
For analog buffer configurations, refer to Cirrus Application Note AN241. Also, a low cost single ended to differential solution is provided on the Customer Evaluation Board.
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CS5368
3.1 Suggested Analog Input Buffer
Figure 7. "Recommended Analog Input Buffer" shows a recommended analog input buffer for a differential to differential topology. For additional configurations, refer to Crystal Application Note number AN241. A low-cost, single-ended (RCA jack) to differential solution is shown in the schematics of the Customer Evalution Board Datasheet (CDB5368).
634
470 pF COG 10 uF AIN+ 100k 10 k COG VQ 10 k 10 uF AIN100k + 470 pF COG 634 91 ADC AIN2700 pF + 91 ADC AIN+
Figure 7. Recommended Analog Input Buffer
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CS5368 4. APPLICATIONS
4.1 Power
For convenient interfacing to external devices, there are five independent power pins for the CS5368. VD powers the digital core. VA powers the analog core. VLS powers the Serial Audio Interface. VLC powers the control logic. VX powers the crystal oscillator. The power pins may have any supported voltage range of the specified voltages supplied simultaneously. To meet full performance specifications, the CS5368 requires normal low noise board layout. The "Typical Connection Diagram" on page 23 shows the recommended power arrangements, with VA connected to a clean supply. VD, which powers the digital filter, may be run from the system logic supply, or it may be powered from the analog supply via a single-pole decoupling filter. Decoupling capacitors should be placed as near to the ADC as possible, with the lower value high frequency capacitors being placed nearest to the device leads. Clocks should be kept away from the FILT+ and VQ pins in order to avoid unwanted coupling into the device. The FILT+ and VQ decoupling capacitors must be positioned to minimize the electrical path to ground. The CDB5368 evaluation board demonstrates an optimum layout for the device.
4.2
Clocking
The device supports clocking through the use of either an on-board crystal oscillator driver or an externally supplied clock. When using the on-board crystal driver, the topology shown in Figure 8. "Crystal Oscillator Topology" must be used. The crystal oscillator manufacturer supplies recommended capacitor values.
XTI XTO
21 22
Figure 8. Crystal Oscillator Topology
When using the on-board crystal oscillator driver, the XTI pin is the input for the Master clock (MCLK) to the device. The XTO pin must not be used to drive anything other than the oscillator tank circuitry. Instead, a buffered copy of XTI is available on the MCLK pin, which is level controlled by VLS and may be used to synchronize other parts to the device. If an external clock is used, the XTI and XTO pins must be grounded, and the MCLK pin becomes an input for the system Master clock. The CS5368 provides on board master clock dividers that precede all other internal clocking. The available dividers are divide by 1, 1.5, 2, 3, 4.
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CS5368
4.3 Stand-Alone Operation
In Stand-Alone Mode, the CS5368 is programmed exclusively with multi-use configuration pins. This mode provides a set of commonly used features. To utilize the complete set of device features, Control-Port Mode needs to be used. To use the CS5368 in Stand-Alone Mode, the configuration pins must be held in a stable state and RST must be asserted until the power supplies and clocks are stable. Upon de-assertion of RST the state of the configuration pins are latched, Vq stabilizes and the device starts sending audio output data.
4.4
Control-Port Operation
In Control-Port Mode, all features of the CS5368 are available. Four multi-use configuration pins become software pins that support the IC or SPI bus protocol. To initiate Control-Port Mode, a controller that supports IC or SPI must be used to enable the internal register functionality. This is done by setting the CP-EN bit (bit 7 of the Global Control Port Register). Once CP-EN is set, all of the device configuration pins are ignored, and the internal register settings determine the operating modes of the part.
4.5
DC Offset Control
The CS5368 includes a dedicated high-pass filter for each channel to remove input DC offset at the system level. If a DC level is present, clicks might be heard when switching between devices in a multichannel system. In Standalone Mode, all of the high pass filters remain enabled. In Control-Port Mode, the high pass filters default to enabled, but may be controlled by writing to the HPF register. If any HPF bit is taken low, the respective high-pass filter is enabled, and it continuously subtracts a measure of the DC offset from the output of the decimation filter. If any HPF bit is taken high during device operation, the value of the DC offset register is frozen, and this DC offset will continue to be subtracted from the conversion result.
4.6
Serial Audio Interface (SAI)
4.6.1 General Description
The SAI port consists of two timing pins, SCLK, LRCK/FS, and four audio data output pins, SDOUT1/TDM, SDOUT2/TDM, SDOUT3/TDMC and SDOUT4/TDMC. The SAI port may be operated as a timing master or a timing slave. The port supplies digital audio data in three standard formats, LJ, IS and TDM. Three sampling ranges are used to provide analog to digital audio conversion from 2 kHz to 216 kHz sampling rates. The main TDM output port resides on the SDOUT1 pin. The remaining three TDM outputs are used to balance device substrate noise. It is recommended that all four of these nets be routed and loaded identically for best device noise performance.
4.6.2 Master and Slave Operation
In Master mode, the CS5368 outputs SCLK and LRCK/FS which are synchronously derived from MCLK. SCLK is the audio clock which shifts out the individual bits of each sample. In LJ and IS format, LRCK/FS signifies which channel of data is being shifted out. In TDM Mode, LRCK/FS acts as a frame synchronization signal. A high transition indicates the beginning of a new frame of 8 channels of serial data. In Slave Mode, SCLK and LRCK/FS become inputs, and the signals must be supplied by another device. The device may be another CS5368 or a microcontroller. Serial data is shifted out by the CS5368 in both cases.
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ADC as timing master
SCLK
Controller
LRCK
ADC as timing slave
SCLK
Controller
LRCK
Figure 9. Master Slave Clock Flow
4.6.3 Synchronization of Multiple Devices
To ensure synchronous sampling in applications where multiple ADCs are used, the MCLK and LRCK must be the same for all of the CS5368s in the system. If only one Master clock source is needed, one solution is to place one CS5368 in Master mode, and slave all of the other devices to the one master. If multiple Master clock sources are needed, a possible solution would be to supply all clocks from the same external source and time the CS5368 reset de-assertion with the falling edge of MCLK. This will ensure that all converters begin sampling on the same clock edge.
Master CS5368
SCLK & LRCK/FS
Slave1 CS5368 Slave2 CS5368 Slave3 CS5368
Figure 10. Master and Slave Clocking for a 32-Channel Application
4.6.4 Sample Rate Ranges
Supported sampling rates are 2 kHz-216 kHz divided into three ranges: 2 kHz-54 kHz, 54 kHz-108 kHz, and 108 kHz-216 kHz. These sampling speed modes are called Single-Speed Mode, Double-Speed Mode and Quad-Speed Mode (SSM, DSM, QSM), respectively.
4.6.5 Using M1 and M0 to Set Sampling Parameters
The Master/Slave operation and the sample rate range are controlled through the settings of the M1 and M0 pins in Stand-Alone Mode, or by the M[1] and M[0] bits in the Global Mode Control Register in ControlPort Mode.
M1 M0 Mode Single-Speed Master Mode Double-Speed Master Mode Quadruple-Speed Master Mode Auto-Detected Speed Slave Mode
Table 2. M1 and M0 Settings
Frequency Range
0 0 1 1
0 1 0 1
2 kHz - 54 kHz 54 kHz - 108 kHz 108 kHz - 216 kHz 2 kHz - 216 kHz
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4.6.6 Using DIF1 and DIF0 to Set Serial Audio Interface Format
The format of the data at the Serial Audio Interface ports is controlled by the settings of the DIF1 and DIF0 pins in standalone mode, or by the DIF[1] and DIF[0] bits in the Global Mode Control Register in ControlPort Mode. .
DIF1 DIF0 Mode
0 0 1 1
0 1 0 1
Left Justified IS TDM (2 wire) TDM (4 wire)
Table 3. DIF1 and DIF0 Pin Settings
4.6.7 Master Mode Audio Clocking
Figure 11. "Master Mode Clock Dividers" shows the configuration of the MCLK dividers and the sample rate dividers while in Master Mode.
S AM P LE R AT E D IV ID E R S
/ 256
S in g le Speed D o u b le Speed Quad Speed
00 01 10
LRCK / FS
M C LK
0 /1
MCLK
D IV ID E R S
0 /1 /1 /2 0 /1 /1 /2
/ 128 / 64
/1 / 1 .5
M1
M0
/4 p in b it C MO D E C MO D E M D IV M D IV 1 n /a M D IV 0 /2 /1
S in g le Speed D o u b le Speed Quad Speed
00 01 10
SCLK
Figure 11. Master Mode Clock Dividers
4.6.8 Slave Mode Audio Clocking
In Slave Mode, the sampling rate is auto-set by examining the incoming MCLK and LRCK/FS signals. LRCK/FS and SCLK operate as inputs in Slave Mode. It is recommended that the LRCK/FS be synchronously derived from the Master clock, and it must be equal to the desired sampling rate, Fs.
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4.6.9 Master and Slave Clock Frequencies
Tables 4 through 9 show the clock speeds for sample rates of 48 kHz, 96 kHz and 192 kHz. In Master Mode, the device outputs the frequencies shown. In Slave Mode, the SCLK/LRCK ratio can be set according to design preference. However, device performance is guaranteed only when using the ratios shown in the tables .
Control Port Mode only
LJ/IS MASTER OR SLAVE
SSM /4 49.152 3.072 1024 64 /3 /2 /1.5 /1
MCLK Divider MCLK (MHz) SCLK(MHz) MCLK/LRCK Ratio SCLK/LRCK Ratio
36.864 3.072 768 64
24.576 3.072 512 64
18.384 3.072 384 64
12.288 3.072 256 64
Table 4. Frequencies for 48 kHz Sample Rate using LJ/IS
LJ/IS MASTER OR SLAVE
DSM /4 49.152 6.144 512 64 /3 /2 /1.5 /1
MCLK Divider MCLK (MHz) SCLK(MHz) MCLK/LRCK Ratio SCLK/LRCK Ratio
36.864 6.144 384 64
24.567 6.144 256 64
18.384 6.144 192 64
12.288 6.144 128 64
Table 5. Frequencies for 96 kHz Sample Rate using LJ/IS
LJ/IS MASTER OR SLAVE
QSM /4 49.152 12.288 256 64 /3 /2 /1.5 /1
MCLK Divider MCLK (MHz) SCLK (MHz) MCLK/LRCK Ratio SCLK/LRCK Ratio
36.864 12.288 192 64
24 12.288 128 64
18.384 12.288 96 64
12.288 12.288 64 64
Table 6. Frequencies for 192 kHz Sample Rate using LJ/IS
TDM MASTER OR SLAVE
SSM /4 49.152 12.288 1024 256 /3 /2 /1.5 /1
MCLK Divider MCLK (MHz) SCLK (MHz) MCLK/FS Ratio SCLK/FS Ratio
36.864 12.288 768 256
24.567 12.288 512 256
18.384 12.288 384 256
12.288 12.288 256 256
Table 7. Frequencies for 48 kHz Sample Rate using TDM
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TDM MASTER OR SLAVE DSM /4 49.152 24.576 512 256 /3 /2 /1.5 /1
MCLK Divider MCLK (MHz) SCLK (MHz) MCLK/FS Ratio SCLK/FS Ratio
36.864 24.576 384 256
24.567 24.576 256 256
18.384 24.576 192 256
12.288 24.576 128 256
Table 8. Frequencies for 96 kHz Sample Rate using TDM
TDM MASTER OR SLAVE
QSM /4 49.152 49.152 256 256 /3 /2 /1.5 /1
MCLK Divider MCLK (MHz) SCLK (MHz) MCLK/FS Ratio SCLK/FS Ratio
36.864 49.152 192 256
24.567 49.152 128 256
18.384 49.152 96 256
12.288 49.152 64 256
Table 9. Frequencies for 192 kHz Sample Rate using TDM
4.7
Serial Audio Formats
The ADC supports IS, Left-Justified and TDM digital interface formats. Audio data should be latched by the receiver on the rising edge of SCLK within the specified setup and hold times.
receiver latches data on rising edges of SCLK
SCLK Even Channels 2,4, ...
LRCK
Odd Channels 1,3, ... MSB
SDOUT
...
LSB
MSB
...
LSB
MSB
Figure 12. LJ Format
receiver latches data on rising edges of SCLK SCLK Even Channels 2,4, ...
LRCK
Odd Channels 1,3, ... MSB
SDOUT
...
LSB
MSB
...
LSB
MSB
Figure 13. IS Format
Bit or Word Wide 256 sclks
FS SCLK LSB MSB
TDM OUT
LSB MSB
LSB MSB
LSB MSB
LSB MSB
LSB MSB
LSB MSB
LSB MSB
LSB MSB
Channel 1 32 clks
Channel 2 32 clks
Channel 3 32 clks
Channel 4 32 clks
Channel 5 32 clks
Channel 6 32 clks
Channel 7 32 clks
Channel 8 32 clks
Figure 14. TDM Format
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4.7.1 LJ and IS FORMAT
The left-justified and IS formats are both two-channel protocols. During one LRCK period, two channels of data are transmitted, odd channels first, then even. The MSB is always clocked out first. In Slave Mode, if more than 32 SCLKs per channel are received from a Master controller, the CS5368 will fill the longer frame with trailing zeroes. If fewer than 24 SCLKs per channel are received from a Master, the CS5368 will truncate the serial data output to the number of SCLKs received.
4.7.2 TDM Format
In TDM Mode, all eight channels of audio data are serially clocked out during a single Frame Sync (FS) cycle. The rising edge of FS signifies the start of a new TDM frame cycle. Each channel slot occupies 32 SCLKs, with the data left justified and with MSB first. TDM output data should both be latched on the rising edge of SCLK within the specified setup and hold times. To achieve maximum noise performance, SDOUT2/TDM should be loaded in the same manner as SDOUT1/TDM. For the same reason, it is also recommended that the serial clock be synchronously derived from the Master clock and be equal to 256xFS.
4.8
Overflow Detection
4.8.1 Stand-Alone Mode
The CS5368 includes overflow detection on all input channels. In Stand-Alone Mode, this information is presented as open drain, active low on the OVFL pin. The pin will go to a logical low as soon as an overrange condition in any channel is detected. The data will remain low, then timeout as specified in "Overflow Timeout" on page 19. After the timeout, the OVFL pin will return to a logical high if there has not been any other overrange condition detected. Note that an overrange condition on any channel will restart the timeout period.
4.8.2 Control-Port Mode
In Control-Port mode, the Overflow Status Register interacts with the Overflow Mask Register to provide interrupt capability for each individual channel. See page 36 for details on these two registers.
4.9
Control Port Operation
The Control Port is used to read and write the internal device registers. It supports two industry standard formats, IC and SPI. The part is in IC format by default. SPI mode is selected if there is ever a high-to-low transition on the AD0/CS pin after the RST pin has been brought high.
4.9.1 SPI Mode
In SPI mode, CS is the CS5368 chip select signal; CCLK is the control port bit clock (input into the CS5368 from a controller); CDIN is the input data line from a controller; CDOUT is the output data line to a controller. Data is clocked in on the rising edge of CCLK and is supplied on the falling edge of CCLK. To write to a register, bring CS low. The first seven bits on CDIN form the chip address and must be 1001111. The eighth bit is a read/write indicator (R/W), which should be low to write. The next eight bits form the Memory Address Pointer (MAP), which is set to the address of the register that is to be updated. The next eight bits are the data which will be placed into the register designated by the MAP. During writes, the CDOUT output stays in the Hi-Z state. It may be externally pulled high or low with a 47 k resistor, if desired.
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There is a MAP auto-increment capability, which is enabled by the INCR bit in the MAP register. If INCR is a zero, the MAP will stay constant for successive read or writes. If INCR is set to a 1, the MAP will auto increment after each byte is read or written, allowing block reads or writes of successive registers. To read a register, the MAP has to be set to the correct address by executing a partial write cycle that finishes (CS high) immediately after the MAP byte. The MAP auto increment bit (INCR) may be set or not, as desired. To begin a read, bring CS low, send out the chip address and set the read/write bit (R/W) high. The next falling edge of CCLK will clock out the MSB of the addressed register (CDOUT will leave the high impedance state). If the MAP auto increment bit is set to 1, the data for successive registers will appear consecutively
.
CS
CC LK C H IP ADDRESS C D IN 1001111 R/W C H IP ADDRESS LSB b y te n MSB LSB MSB LSB
MAP MSB
DATA
1001111
R/W
b y te 1 High Impedance CDOUT
MAP = Memory Address Pointer, 8 bits, MSB first
Figure 15. SPI Format
4.9.2 IC Mode
In IC mode, SDA is a bidirectional data line. Data is clocked into and out of the part by the clock, SCL. There is no CS pin. Pins AD0 and AD1 form the two least significant bits of the chip address and should be connected through a resistor to VLC or DGND as desired. The state of the pins is latched when the CS5368 is being released from RST. A Start condition is defined as a falling transition of SDA while SCL is high. A Stop condition is a rising transition of SDA while SCL is high. All other transitions of SDA occur while SCL is low. The first byte sent to the CS5368 after a Start condition consists of a 7-bit chip address field and a R/W bit (high for a read, low for a write). The upper five bits of the 7-bit address field are fixed at 10011. To communicate with a CS5368, the chip address field, which is the first byte sent to the CS5368, should match 10011 and be followed by the settings of the AD1 and AD0. The eighth bit of the address is the R/W bit. If the operation is a write, the next byte is the Memory Address Pointer (MAP) which selects the register to be read or written. If the operation is a read, the contents of the register pointed to by the MAP will be output. Setting the auto increment bit in MAP allows successive reads or writes of consecutive registers. Each byte is separated by an acknowledge bit. The ACK bit is output from the CS5368 after each input byte is read and is input to the CS5368 from the microcontroller after each transmitted byte. Since the read operation cannot set the MAP, an aborted write operation is used as a preamble. The write operation is aborted after the acknowledge for the MAP byte by sending a Stop condition. The following pseudocode illustrates an aborted write operation followed by a read operation. Send start condition. Send 10011xx0 (chip address & write operation). Receive acknowledge bit. Send MAP byte, auto increment off. Receive acknowledge bit.
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Send stop condition, aborting write. Send start condition. Send 10011xx1 (chip address & read operation). Receive acknowledge bit. Receive byte, contents of selected register. Send acknowledge bit. Send stop condition.
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
19
24 25 26 27 28
SCL
CHIP ADDRESS (WRITE) MAP BYTE
INCR
DATA
2 1 0 7 6 1 0 7
DATA +1
6 1 0 7
DATA +n
6 1 0
SDA
START
1
0
0
1
1 AD1 AD0 0
6
5
4
3
ACK
ACK
ACK
ACK STOP
Figure 16. IC Write Format
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
SCL
CHIP ADDRESS (WRITE) MAP BYTE
INCR
STOP
1 0 1
CHIP ADDRESS (READ)
0 0 1 1 AD1 AD0 1
DATA
7 0
DATA +1
7 0
DATA + n
7 0
SDA
1
0
0
1
1 AD1 AD0 0
6
5
4
3
2
ACK START
ACK START
ACK
ACK
NO ACK
STOP
Figure 17. IC Read Format
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CS5368 5. REGISTER MAP
In Control Port Mode, the bits in these registers are used to control all of the programmable features of the ADC.
5.1
Adr
Register Quick Reference
Name 7 6 5 4 3 2 1 0
00 01 02 03 04 05 06 07 08 09 0A
REVI GCTL OVFL OVFM HPF
RESERVED
CHIP-ID[3:0] CP-EN OVFL8 OVFM8 HPF8 not used MUTE8 MUTE7 not used CLKMODE OVFL7 OVFM7 HPF7 MDIV[1:0] OVFL6 OVFM6 HPF6 MUTE6 OVFL5 OVFM5 HPF5 MUTE5 DIF[1:0] OVFL4 OVFM4 HPF4 PDN87 MUTE4 SDEN4
REVISION[3:0] MODE[1:0] OVFL2 OVFM2 HPF2 PDN43 MUTE2 SDEN2 OVFL1 OVFM1 HPF1 PDN21 MUTE1 SDEN1 OVFL3 OVFM3 HPF3 PDN65 MUTE3 SDEN3
PDNE
RESERVED
PDN-BG PDN-OSC
MUTE
RESERVED
SDEN
5.2
R
00h (REVI) Chip ID Code & Revision Register
R/W 7 6 5 4 3 2 1 0
CHIP-ID[3:0]
REVISION[3:0]
Default: See description The Chip ID Code & Revision Register is used to store the ID and revision of the chip. Bits[7:4] contain the chip ID, where the CS5368 is represented with a value of 0x8. Bits[3:0] contain the revision of the chip, where revision A is represented as 0x0, revision B is represented as 0x1, etc.
5.3
01h (GCTL) Global Mode Control Register
R/W 7 6 5 4 3 2 1 0
R/W
CP-EN
CLKMODE
MDIV[1:0]
DIF[1:0]
MODE[1:0]
Default:
0x00
The Global Mode Control Register is used to control the Master/Slave Speed modes, the serial audio data format and the Master clock dividers for all channels. It also contains a control port enable bit. Bit[7] CP-EN manages the Control Port Mode. Until this bit is asserted, all pins behave as if in Stand-Alone Mode. When this bit is asserted, all pins used in Stand-Alone Mode are ignored, and the corresponding register values become functional.
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Bit[6] CLKMODE Setting this bit puts the part in 384X mode (divides XTI by 1.5), and clearing the bit invokes 256X mode (divide XTI by 1.0 - pass through). Bits[5:4] MDIV[1:0] Each bit selects an XTI divider. When either bit is low, an XTI divide by 1 function is selected. When either bit is HIGH, an XTI divide by 2 function is selected. With both bits HIGH, XTI is divided by 4. The table below shows the composite XTI division using both CLKMODE and MDIV[1:0].
CLKMODE,MDIV[1],MDIV[0] 000 100 001 or 010 101 or 110 011 111 DESCRIPTION Divide-by-1 Divide-by-1.5 Divide-by-2 Divide-by-3 Divide-by-4 Unused
Bits[3:2] DIF[1:0] Determine which data format the serial audio interface is using to clock out data. DIF[1:0] 0x00 Left Justified format 0x01 IS format 0x02 TDM format 0x03 TDM format Bits[1:0] MODE[1:0] This bit field determines the device sample rate range and whether it is operating as an audio clocking Master or Slave. MODE[1:0] 0x00 Single-Speed Mode Master 0x01 Double-Speed Mode Master 0x02 Quad-Speed Mode Master 0x03 Slave Mode all speeds
5.4
R
02h (OVFL) Overflow Status Register
R/W 7 6 5 4 3 2 1 0
OVFL8
OVFL7
OVFL6
OVFL5
OVFL4
OVFL3
OVFL2
OVFL1
Default:
Note:
0xFF, no overflows have occurred.
This register interacts with Register 03h, the Overflow Mask Register.
The Overflow Status Register is used to indicate an individual overflow in a channel. If an overflow condition on any channel is detected, the corresponding bit in this register is asserted (low) in addition to the open drain active low OVFL pin going low. Each overflow status bit is sticky and is cleared only when read, providing full interrupt capability.
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5.5 03h (OVFM) Overflow Mask Register
R/W 7 6 5 4 3 2 1 0
R/W
OVFM8
OVFM7
OVFM6
OVFM5
OVFM4
OVFM3
OVFM2
OVFM1
Default:
0xFF, all overflow interrupts enabled.
The Overflow Mask Register is used to allow or prevent individual channel overflow events from creating activity on the OVFL pin. When a particular bit is set low in the Mask register, the corresponding overflow bit in the Overflow Status register is prevented from causing any activity on the OVFL pin.
5.6
04h (HPF) High-Pass Filter Register
R/W 7 6 5 4 3 2 1 0
R/W
HPF8
HPF7
HPF6
HPF5
HPF4
HPF3
HPF2
HPF1
Default:
0x00, all high-pass filters enabled.
The High-Pass Filter Register is used to enable or disable a high-pass filter that exists for each channel. These filters are used to perform DC offset calibration, a procedure that is detailed in
"DC Offset Control" on page 26.
5.7
05h Reserved
R/W 7 6 5 4 3 2 1 0
Reserved
-
-
-
-
-
-
-
-
5.8
06h (PDN) Power Down Register
R/W 7 6 5 4 3 2 1 0
R/W
RESERVED
PDN-BG
PDN-OSC
PDN87
PDN65
PDN43
PDN21
Default:
0x00 - everything powered up
The Power Down Register is used as needed to reduce the chip's power consumption. Bit[7] RESERVED Bit[6] RESERVED Bit[5] PDN-BG When set, this bit powers-down the bandgap reference. Bit[4] PDN-OSC controls power to the internal oscillator core. When asserted, the internal oscillator core is shut down, and no clock is supplied to the chip. If the chip is running off an externally supplied clock at the MCLK pin, it is also prevented from clocking the device internally. Bit[3:0] PDN When any bit is set, all clocks going to a channel pair are turned off, and the serial data outputs are forced to all zeroes.
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5.9 07h Reserved
R/W 7 6 5 4 3 2 1 0
Reserved
-
-
-
-
-
-
-
-
5.10
08h (MUTE) Mute Control Register
7 6 5 4 3 2 1 0
R/W
R/W
MUTE8
MUTE7
MUTE6
MUTE5
MUTE4
MUTE3
MUTE2
MUTE1
Default:
0x00, no channels are muted.
The Mute Control Register is used to mute or un-mute the serial audio data output of individual channels. When a bit is set, that channel's serial data is muted by forcing the output to all zeroes.
5.11
09h Reserved
7 6 5 4 3 2 1 0
R/W
Reserved
-
-
-
-
-
-
-
-
5.12
0Ah (SDEN) SDOUT Enable Control Register
7 6 5 4 3 2 1 0
R/W
R/W
unused
SDEN4
SDEN3
SDEN2
SDEN1
Default:
0x00, all SDOUT pins enabled.
The SDOUT Enable Control Register is used to tri-state the serial audio data output pins. Each bit, when set, tri-states the associated SDOUT pin.
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Appendix A Digital Filter Plots
0.1 0.08
0.06
0.04
Amplitude (dB)
0.02
0
-0.02
-0.04
-0.06
-0.08
-0.1
0
0.05
0.1
0.15
0.2 0.25 0.3 Frequency (normalized to Fs)
0.35
0.4
0.45
0.5
Figure 18. SSM Passband
0.1
0.08
0.06
0.04
Amplitude (dB)
0.02
0
-0.02
-0.04
-0.06
-0.08
-0.1
0
0.05
0.1
0.15
0.2 0.25 0.3 Frequency (normalized to Fs)
0.35
0.4
0.45
0.5
Figure 19. DSM Passband
0.1
0.08
0.06
0.04
Amplitude (dB)
0.02
0
-0.02
-0.04
-0.06
-0.08
-0.1
0
0.05
0.1 0.15 Frequency (normalized to Fs)
0.2
0.25
Figure 20. QSM Passband
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0
-20
-40
Amplitude (dB)
-60
-80
-100
-120
-140
0
0.1
0.2
0.3
0.4 0.5 0.6 Frequency (normalized to Fs)
0.7
0.8
0.9
1
Figure 21. SSM Stopband
0
-20
-40
Amplitude (dB)
-60
-80
-100
-120
-140
0
0.1
0.2
0.3
0.4 0.5 0.6 Frequency (normalized to Fs)
0.7
0.8
0.9
1
Figure 22. DSM Stopband
0
-20
-40
Amplitude (dB)
-60
-80
-100
-120
0
0.1
0.2
0.3
0.4 0.5 0.6 Frequency (normalized to Fs)
0.7
0.8
0.9
1
Figure 23. QSM Stopband
40
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0
-0.2
-0.4
-0.6
Amplitude (dB)
-0.8
-1
-1.2
-1.4
-1.6
-1.8
-2 0.4
0.42
0.44
0.46
0.48 0.5 0.52 Frequency (normalized to Fs)
0.54
0.56
0.58
0.6
Figure 24. SSM -1 dB Cutoff
0
-0.2
-0.4
-0.6
Amplitude (dB)
-0.8
-1
-1.2
-1.4
-1.6
-1.8
-2 0.4
0.42
0.44
0.46
0.48 0.5 0.52 Frequency (normalized to Fs)
0.54
0.56
0.58
0.6
Figure 25. DSM -1 dB Cutoff
0
-0.2
-0.4
-0.6
Amplitude (dB)
-0.8
-1
-1.2
-1.4
-1.6
-1.8
-2 0.2
0.22
0.24
0.26
0.28 0.3 0.32 Frequency (normalized to Fs)
0.34
0.36
0.38
0.4
Figure 26. QSM -1 dB Cutoff
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Appendix B Parameter Definitions
Dynamic Range
The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. Dynamic Range is a signal-to-noise ratio measurement over the specified bandwidth made with a -60 dBFS signal. 60 dB is added to resulting measurement to refer the measurement to full-scale. This technique ensures that the distortion components are below the noise level and do not affect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-199, and the Electronic Industries Association of Japan, EIAJ CP-307. Expressed in decibels. The dynamic range is specified with and without an A-weighting filter.
Total Harmonic Distortion + Noise
The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Measured at -1 and -20 dBFS as suggested in AES17-1991 Annex A. Specified using an A-weighting filter.
Frequency Response
A measure of the amplitude response variation from 10 Hz to 20 kHz relative to the amplitude response at 1 kHz. Units in decibels.
Interchannel Isolation
A measure of crosstalk between one channel and all remaining channels, measured for each channel at the converter's output with no signal to the input under test and a full-scale signal applied to all other channels. Units in decibels.
Interchannel Gain Mismatch
The gain difference between left and right channels. Units in decibels.
Gain Error
The deviation from the nominal full-scale analog output for a full-scale digital input.
Gain Drift
The change in gain value with temperature. Units in ppm/C.
Offset Error
The deviation of the mid-scale transition (111...111 to 000...000) from the ideal. Units in mV.
Intrachannel Phase Deviation
The deviation from linear phase within a given channel.
Interchannel Phase Deviation
The difference in phase response between channels. .
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Appendix C Package Dimensions
48L LQFP PACKAGE DRAWING
E E1
D D1
1
e
B A A1
L
DIM A A1 B D D1 E E1 e* L
MIN --0.002 0.007 0.343 0.272 0.343 0.272 0.016 0.018 0.000
INCHES NOM 0.055 0.004 0.009 0.354 0.28 0.354 0.28 0.020 0.24 4
MAX 0.063 0.006 0.011 0.366 0.280 0.366 0.280 0.024 0.030 7.000
MIN --0.05 0.17 8.70 6.90 8.70 6.90 0.40 0.45 0.00
MILLIMETERS NOM 1.40 0.10 0.22 9.0 BSC 7.0 BSC 9.0 BSC 7.0 BSC 0.50 BSC 0.60 4
MAX 1.60 0.15 0.27 9.30 7.10 9.30 7.10 0.60 0.75 7.00
* Nominal pin pitch is 0.50 mm Controlling dimension is mm. JEDEC Designation: MS026
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Table 10. Revision History
Revision
Date
Changes
A1
July 2005
Initial Release
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find one nearest you go to http://www.cirrus.com/
IMPORTANT NOTICE "Advance" product information describes products that are in development and subject to development changes. Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. SPI is a trademark of Motorola, Inc.
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